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SN74AUP1G74: Can CLK be held high?

Chris Krasnichuk1
Prodigy 460 points
Part Number: SN74AUP1G74

Hi Folks,

Customer would like to use the SN74AUP1G74 to latch a signal during power-on.

Here’s a snapshot of the circuit:

 

The question is regarding the power on reset signal connection to the clock input of the device. 

The POR_L signal will be low while power rails come up, but as soon as all rails are stable + ~100ms delay, the POR_L signal will go high and stay high as long as the board is powered.

Is it valid to have the clock signal transition low to high once (this will clock in the D value of logic 1) and then stay high continually afterward?

It's probably not a problem however leaving the clock high is not shown as one of the functional modes of the device (see below)

 

Can we confirm the mode of operation with clock always high is valid?

  • +1
    TI__Guru* 96681 points

    Hi Chris,

    Yes, the CLK pin can be held high or low. Data is loaded when the clock transitions from low to high, which is indicated by the 'up arrow' in the function table. Also, this is the function of a 'flip flop' (edge triggered) as opposed to a 'latch' (level triggered).

    The PRE\ and CLR\ inputs are asynchronous and can be used to turn this device essentially into an RS latch while D and CLK are held at a constant state.