Hello Folks,
I have one question about logic gate (AND)
I have seen that in the datasheet is written: "Schmitt Trigger Action at All Inputs Makes the Circuit Tolerant for Slower Input Rise and Fall Time"
But when i check the rest of the datasheet, it is not given the threshold window ( ΔVT Hysteresis) or any picture illustrating that. Is there any reason behind?
Thanks in Advance!
Tobias