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74AUP1G80 additive jitter range

Ian Jin
Prodigy 110 points

Hi, 

If I use 74AUP1G80 as a clock divider (DIV2, connect the /Q to D), what gonna be the additive jitter of the output clock in ps over the input clock? just roughly.

The Vcc is 3.3V, at room temperature  25 degreeC.

And what about the 74AUC1G80 at 2.5V Vcc?

Thank you.

 

  • 0
    TI__Mastermind 46480 points

      Hi Ian

     I dont have any jitter data for these devices, however whe you use them as a divider you will reduce the jitter usually making it insignificant.

     

  • 0 in reply to Chris Cockrill
    Prodigy 110 points

    Hi Chris,

    Thank you for your reply.

    Actually I just want to know the additive jitter performance of those flip-flops. For example, if I generate a PWM signal or other signal by a group of logic and the last stage is a flip-flop,that is the very common application of a flip-flip, what's the additional jitter in that signal over the system clock will be?

    Usually I use a FPGA to generate those signals, but the jitter performance of a FPGA output is not so good. So I suspect If I use a flip-flop, especially the AUP or AUC little logic family, at the last stage to re-clock the signal with the system clock, it might get the better performance.  That is why I ask the question.

    Setup the flip-flop as a 2 divider is the easiest way to measure that performance by compairing with the input and output clock.  If anybody did the test or has some releated experience, please let me know the result.  Thank you.  

    Ian

     

  • 0 in reply to Chris Cockrill
    Prodigy 110 points

    Hi Chris,

    Did you find some answer?

    Thanks,

    Ian

  • 0 in reply to Ian Jin
    TI__Mastermind 46480 points

    I was not able to find jitter data on any AUP device