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Original question:

About OE polarity of the SN74LV126A.

SN74LV126A: Datasheet

Ray Vincent Aranzaso
Mastermind 18180 points
Part Number: SN74LV126A

Hi,

Good Day.

I'm looking at the SN74LV126A datasheet.

It says "The SN74LV126A devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.

Each output is disabled when the associated output-enable (OE) input is low.

When OE is high, the respective gate passes the data from the A input to its Y output."

But table 1 indicates the opposite. Which is correct?

I found 2 posts related to this. Please help to check the link below.

https://e2e.ti.com/support/logic-group/logic/f/logic-forum/439470/about-oe-polarity-of-the-sn74lv126a?tisearch=e2e-sitesearch&keymatch=SN74LV126A%252520datasheet#

https://e2e.ti.com/support/logic-group/logic/f/logic-forum/695996/sn74lv126a-sn74lv126a-oe?tisearch=e2e-sitesearch&keymatch=SN74LV126A%20datasheet#

Best Regards,

Ray Vincent

  • 0
    TI__Guru* 97046 points

    Hi Ray,

    Thanks for bringing up the additional threads; I will prioritize this update to reduce confusion among our customers.

    The '126 logic function is standard across the industry, and the correct information, applicable to all SN74____126 devices, follows: