Hello TI Experts,
We have a faulty design (which have already been mass shipped out in field ….), we want to evaluate the risk of the design and consider next step
Conditions:
1. SN74LVC244APWR
- 3.3V power supply
- Two not used high output GATEs (input is PU) are directly connect to GND (bad design)
- All the other remaining Gates have very small current consumption, less than 1mA
As the following picture:
Questions:
What is the consequence? Will this damage the whole chip or only that two gate? We can accept if only that two gates are damaged as they do not carry any function
Thanks
Eric Wang