SN74AUC1GU04: Performance comparison

That answers point 1. AUC is fascinating.

Quite evidently my overall question was about the fastest ring oscillator. I only became curious when I noticed that it seems _not_ to be the triple unbuffered inverter (which it is in other logic families AFAICS).

As I see it now - max delays being not necessarily a reliable indicator for a ring oscillator AFAIK - the best candidates might be the Dual-EXOR or a hex buffered inverter. Would you agree? 

I mean this question really requires some FAE support in this case that deviates from the usual experience.

I can do lots of trial and error, but I have to explain it to my superiors too ...

I expect the specified maximum propagation delay to include a large safety factor, and this factor might be different, depending on the measurement or modelling methods. The actual propagation delays are likely to be much more similar between these devices, and I would not rule out that unbuffered invertes are faster.

Comparing the typical t_pd shown in SCEA027 and SCEA033 appears to show that a larger package result in larger delay, at least for small loads. This can be explained by the larger capacitance/inductance.

Do we know that a dual-EXOR loop with one gate inverting and the other buffering would oscillate at all?

A single unbuffered inverter does not, a triple usually does. With the 2-EXOR-approach we are in the middle and somehow in unknown territory. Not even Google found such a design. (Few components combine matched inverters and buffers.)

But for me frequency matters, because I need to minimize a coupling capacitance later in the chain.

It is pretty difficult to create two fast complementary "carrier" signals with an inverter ring oscillator (but may be possible with two coupled 3-rings), therefore the EXOR-approach has charme. 

Nominally I'd say yes, but could there be distortions i.e. different rise and fall delays?

A max value in the DS would not rule that out, and I'd very much like to end up with a duty cycle near 50%.

Here some knowledge about the internal structure might help. And picoseconds do matter already.

ps (i.e. 100s of tghem) matter only in matching the edges for proper duty-cycle. Luckily the absolute frequency for me is quite irrelevant. 

And I do look at the limits of standard logic for cost reasons. The magic is to use these components boldly where no one has gone before, kind of. It is possible if you think analog, we are getting down to the transistor level with its non-idealities. But coping with such limits, that's engineering. Standard logic covers the range up to ca. 300MHz, I believe the useful frequency range can at least be doubled for some clever applications. That's what I am after and I am sure about it, but sometimes I have to ask inquisitive questions...

Returning to my open question from above: Did anyone (at TI) ever bother to build a ring oscillator with a dual EXOR, particularly in AUC? Evidently no clean logic levels will come out of it and processing those signals will also need linear design techniques, but unbuffered inverters (and fast analog switches) give me access to an advanced technology node that else is available only for IC-designers. That's the trick.

I even consider DIY-flipflops with a performance above the AUC74, a DLL and similar stuff. If TI only knew what it is good for...!

Hey Alfred,

Alfred Fuchs1 said:

And I do look at the limits of standard logic for cost reasons. The magic is to use these components boldly where no one has gone before, kind of. It is possible if you think analog, we are getting down to the transistor level with its non-idealities. But coping with such limits, that's engineering. Standard logic covers the range up to ca. 300MHz, I believe the useful frequency range can at least be doubled for some clever applications. That's what I am after and I am sure about it, but sometimes I have to ask inquisitive questions...

Having worked at TI a long time now, the problem I see with this approach is that when TI makes a change to the device still within the datasheet specs, whether intentional or not, it will often result in your design failing. We regularly have customers come to us with designs that were based on the typical performance rather than the corner performance / datasheet limits, and those returns are denied. It can cost your company in the long run to not design circuits with appropriate limits. Feel free to ignore me here, but you will likely take on liability for failures.

Alfred Fuchs1 said:

Returning to my open question from above: Did anyone (at TI) ever bother to build a ring oscillator with a dual EXOR, particularly in AUC? Evidently no clean logic levels will come out of it and processing those signals will also need linear design techniques, but unbuffered inverters (and fast analog switches) give me access to an advanced technology node that else is available only for IC-designers. That's the trick.

They may have, but I do not have any records showing that.

Alfred Fuchs1 said:

If TI only knew what it is good for...!

We certainly do - but we also know the limits of IC manufacturing from many decades of experience -- and just from my personal experience, I can say many customers have ended up in a bad situation due to these types of design practices.

Hey Alfred,

No offense intended - I see this often on returns here, which is why I harp on it so much. I hate to see any of our customers get frustrated when we won't accept a return due to operation outside the DS spec. I've been in this role about 8 years now, and have handled many thousands of customer interactions.

I also use devices well outside DS spec, but only on home projects where it's only my cheap design that is risked. Haven't had any issues yet with my designs, but TI is very risk averse - ie our datasheets will likely always be very conservative.