Our current design is shown in the figure.
Before the FPGA is started and the configuration is completed, the GPIO of the FPGA has a built-in 75K pull-up resistor.
If the pull-down resistor is not added to the B port, then the B port will be high. However, we want the B port to be low before the FPGA configuration is complete.
Therefore, we added a pull-down resistor on the B port.
In debugging, we found that. When the pull-down resistor is 100K, the B port may also be high when the system is powered on. When the pull-down resistance is continuously reduced to about 22K. When the system is powered on, the B port is always kept low. I would like to ask, is there any theoretical support for the value of the pull-down resistor?