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TXS0104E: Questions of TXS0104E

Jimmy Lai
Expert 6845 points
Part Number: TXS0104E

Dear Team,

1. The output of the chip has a capacitive load limit: do not exceed the requirement of 30ns for one trigger. However, as shown in the circuit shown in the figure below, QSPI_RST adds a 0.1uF capacitor to ground, and the actual high and low level change time of the signal is about 0.6ms. Please confirm its impact, and is it possible not to care about the 30ns requirement?
2. As shown in 9.3.5, when the Output is high, there is a 4k pull-up resistor. If the following circuit signal is added with a 1k pull-down, will the actual output high level be 1/5 VCCA (half-high level) and cause the signal to work abnormally? 

Many Thanks,

Jimmy

  • 0
    Guru 317370 points

    1. The circuit image did not attach. Anyway, when you exceed the capacitance limit, the edge accelerator will not be able to complete raise the output voltage, and the rest of the rising edge will be much slower because the line is pulled high only by the pull-up resistor.

    2. The TXS0104E always has 10 kΩ resistors. You must never use pull-down resistors with TXS/LSF devices because the high output voltage is generated only by the pull-up resistors.

    I do not know your circuit, but unidirectional signals would be handled better with unidirectional translators like the TXU0x0x.

  • 0 in reply to Clemens Ladisch
    TI__Expert 6845 points

    Hi Ladisch,

    Please refer below, thanks.

    Jimmy

  • 0 in reply to Jimmy Lai
    TI__Guru 51816 points

    Hi Jimmy,

    Yes, slower rise/fall times may impact the one-shots to time-out per its' designed duration prior to the internal 10K pulling the line HIGH for a valid output level.

    I also see you have a pull-up on the output which is stronger. Please share the waveform for what is observed at the output.

    Also help see Effects of pull-ups on TXS clarifying how stronger pull-ups impact the output levels for higher VOL, thanks.

    Best Regards,

    Michael.