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SN74LVC1G08: The rising edge of the input signal is slow, causing the output signal to jitter

Part Number: SN74LVC1G08
Other Parts Discussed in Thread: SN74AHC1G08

Hi Team,

Measuring the output pin of the device, find that the output signal jitter violently when the input signal is normal. The troubleshooting found that the input pin of the buffer, the rising edge of pin3 is relatively slow. The rise time of Pin3 is about 2.6ms. 

I want to ask, what is the rise time limit of the input signal for SN74LVC1G08? That is, how many ms does the signal rise time be less than without producing a phenomenon similar to signal jitter?

The schematic:

The test waveform of output signal:

Thanks,

Gust

  • Hi Gust,

    Typically, CMOS input transition times need to be faster than what you are experiencing. For the SN74LVC1G08 the given transition rate for Vcc = 3.3V is 10 ns/V. For slow inputs, devices with Schmitt trigger inputs, like the SN74AHC1G08, are preferred. Check out this Application Report on the topic for additional information.