Team,
I'm surprised to not find more data on the saturation level of the input-output switch of this family of level shifters in the datasheet. from https://www.ti.com/lit/an/slva675b/slva675b.pdf figure4 . I'm guessing that in the HW configuration described figure 2 of the same document, I'm guessing that the opening of the switch starts around 0.8V to end around 1.3V: am I correct ?
Is there a way to find this information anywhere else?
thanks for the video, it's crazy how the simplest devices are usually the toughest to grasp. So typical FET threhold in both direction A>B as B.A is 0.8V. can we get any feel for the spread of this parameter against aging/process variation / temperature.
this is critical for TIer1s to justify their deisgn to car oem.
I agree - this device and ones like it generate more technical questions than most other device.
The 0.8V threshold voltage itself is not specified in the datasheet- this is part of the design of the internal FET since it is in a diode- like configuration and is not required to know this Vth value in order to operate the device. The value of the RON is more crucial as they determine the timing specs and allow for lower VOL levels seen at the output.
I agree with Jack here but thought I could provide a little more insight as to why you can (mostly) ignore the gate threshold in this circuit.
The LSF010x series of translators only include transistors in the IC (dotted box), while the LSF0204 incorporates a bit more inside (red box). Ignoring the enable circuitry (since it doesn't affect the bias), the 200kohm resistor and external diode-connection of the bias channel are moved internal for the LSF0204, so it makes the translator easier to use by eliminating that external bias circuit.
Because the channel transistors are on the same die, we can expect that their characteristics will remain very closely matched across PVT, and the gate threshold can essentially be designed out of the equation for the translation circuit. That is - assuming you have enough difference between Vref_A and Vref_B to provide sufficient bias -- which is at least 0.8 V:
Speaking more mathematically:
The gate voltage (ref to gnd) of the bias transistor will be:
(Eq 1) V_G = VCCA + (V_tn + V_od)
V_tn being the gate threshold voltage, and V_od being the over-drive voltage for the given bias condition.
We assume V_od is very small since we bias at only a few micro-amps, so let's replace that with zero and we get:
(Eq 1a) V_G = VCCA + V_tn
Looking at any other channel transistor, the gate voltage is the same (they are wired together internally), so when determining the state of one of the channel transistors we can use the following:
(Eq 2) V_GS = V_G - V_S
V_G being the same as the first gate, and V_S being the lower of the two voltages between V(A1) and V(B1) in the drawing above.
Substituting Eq 1a into Eq 2:
(Eq 3) V_GS = VCCA + V_tn - V_S
Device is in cutoff if Eq 4 is met:
(Eq 4) V_GS < V_tn
Sub Eq 3 into Eq 4:
VCCA + V_tn - V_S < V_tn
Subtract V_tn from both sides...
VCCA - V_S < 0
And rearrange a bit
V_S > VCCA
Which nicely explains how the device really works -- if the input is above VCCA, the nFET is turned off, and when the input is less than VCCA, the nFET is turned on.
V_tn plays no part in the actual translation -- with the exception of having enough voltage difference between VCCA and VCCB to support it (at least 0.8 V).
