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LSF0102: LSF0102 VOL level

user5143197
Prodigy 120 points
Part Number: LSF0102

Hi team,

In the following configuration, I think it is necessary to design the maximum value of the voltage level input to the FPGA (the maximum value of VOL of LSF0102) to be lower than the maximum value of VIL of the FPGA. However, considering the ASIC (driver) VOL = 0.4V and the voltage drop due to LSF0102 = 0.35V, it becomes 0.4V + 0.35V = 0.75V, which does not satisfy the FPGA VOL = 0.63V. Is this idea correct? Actually, the sink current is less than 15mA, but is there any information about how much voltage drop will occur due to LSF0102 when the sink current is less than 15mA (for example, 8mA) ?

Best regards,

Toshi

  • 0
    Guru 316920 points

    MOSFETs have a constant drain-to-source resistance (if they are not overloaded). So you can model the ASIC output as a 0.4 V / 8 mA = 50 Ω resistor to ground. And the LSF can be modelled as a 0.35 / 15 mA = 23.3 Ω resistor. So the FPGA's actual input voltage will be about 0.2 V.