Hello,
Our design uses CD74HC173s and we are currently verifying our Failure Mode & Effect Analysis with some tests.
In our test condition, \OE & \E signals are grounded, so they are always enabled. The output signals are pulled-up because they control active low bus switches.
The purpose of this test is verifying the output when the board is powered up while input (D) and clock signal (CP) are in LOW condition.
According to the datasheet, output shall be Q0 if the clock is in LOW condition.
For that reason, we expected that the output is HIGH condition because there are pulled-up resistors.
However, the output goes LOW for ~4ms, then goes back to High condition.
Is this normal behavior of the component? or the component does not have the guaranteed output without clock rising edge after it is powered up.
