Hello,
Are there any adverse effects if I disable VCC to the SN54SC6T17-SEP while its inputs are still being driven from, e.g., an FPGA? Is there a difference if I just leave VCC open vs. tying VCC to ground?
Thanks,
Rob
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Hello,
Are there any adverse effects if I disable VCC to the SN54SC6T17-SEP while its inputs are still being driven from, e.g., an FPGA? Is there a difference if I just leave VCC open vs. tying VCC to ground?
Thanks,
Rob
Hi Clemens,
Thanks for pointing me to that FAQ, now I have a more complete picture:
Thanks,
Rob
[1] [FAQ] Can the input voltage (Vi) to my logic device be higher than the supply voltage (Vcc)?
e2e.ti.com/.../faq-can-the-input-voltage-vi-to-my-logic-device-be-higher-than-the-supply-voltage-vcc
[2] Logic in Live-Insertion Applications with a Focus on GTLP
www.ti.com/.../scea026.pdf