Hello:
Please assist in conducting a review of the MC project schematic about SN74LVC1G74
Due to the urgency of the project, we hope to receive feedback as soon as possible. Thanks!!!

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Hello:
Please assist in conducting a review of the MC project schematic about SN74LVC1G74
Due to the urgency of the project, we hope to receive feedback as soon as possible. Thanks!!!

The schematic looks ok. It depends on the transition time of the signal on the D pin: the RC delay created from the resistor on /Q and the capacitor could violate input transition rate requirements.
Hi Malcolm:
Regarding SN74LVC1G74, What are the appropriate pull-up resistance values for the D pin and/PRE pin, respectively?
That depends, see here: (+) [FAQ] How do I size pull-up or pull-down resistors? - Logic forum - Logic - TI E2E support forums
For the D pin it depends on how it effects the rise time of the signal. That would be something you'd have to measure.