TXS0104E: without input, output side getting clk

Sathya Priya

Prodigy 170 points

Part Number: TXS0104E

Tool/software:

Hi Team,

We are using the Level translator IC TXS0104EYZTR, we are facing one issue.

without clock in 1.8V side, 3.3V side we are getting clock high 3.3V.

Regards,

Sathya Priya N

4 months ago

0 Clemens Ladisch 4 months ago

Guru 272490 points

This is to be expected. The pull-up resistors pull the lines up. (The TXS also has internal pull-ups; you can remove the external ones.)

To disable all outputs, you would have to pull OE low.

0 Jack Guan 4 months ago

TI__Mastermind 23651 points

Hey Sathya,

Similar to what Clemens' mentioned, this is expected due to the internal pullups of the TXS. You may also remove external pullups in the schematic as well to avoid creating a voltage divider with the internal pullups.

Regards,
Jack

0 Sathya Priya 4 months ago in reply to Jack Guan

Prodigy 170 points

Hi Clemens and Jack,

Thanks for the input. We will try to remove the external pull up and try testing it.

Regards,

Sathya Priya N

0 Clemens Ladisch 4 months ago in reply to Sathya Priya

Guru 272490 points

That will not change the behaviour because there still is the internal pull-up.

What output signal do you want to see?

Logic

Logic forum

TXS0104E: without input, output side getting clk