SN74HCT273: SN74HCT273PWR Product performance consulting

This change is described in PCN#20220328001.1. The new die is an entirely new design, with timing characteristics similar to those of the SN74HCS273. However, the limits guaranteed by the datasheet have not changed.

I would guess that your circuit relies on the flip-flops being slow and violates the setup/hold time limits. Please show an oscilloscope trace of the relevant CLK/D/Q signals.

Hi

Please check the oscilloscope picture
thank you

A time base if 1 ms is not suitable for analyzing timing relationships. Please zoom in on the point where you think the output behaves incorrectly.

Hi
Because there are too many signals, I can't find the wrong point, and it is a little disorganized, and the error is a little messy, and another one will report an error after repairing, but the use of the previous logo with printing will not appear such a situation

In this trace, the behaviour is correct: on the rising edge of CLK, the input is copied to the output.

I do not know your circuit, or what it is supposed to do, or how the inputs signals are generated. But the only way that the observed behaviour could change is when some D input is changing at the same time when a rising edge on CLK happens.

Where do the D and CLK signals come from? Are they generated in software (GPIOs) or hardware?

Hi

This is the result of altera's cpld

Hi
Since our entire production line has stopped, could you arrange a Chinese technology to communicate with us over the phone
thank you

Hi Yingjiao,

Would you be able to supply a schematic of this design? If you are able to give some additional details we can consider setting up a call in the future. However, without more information a call would not be helpful. We need to see a schematic as well as oscilloscope traces where the design is not working as intended at the minimum.

Best,

Malcolm

Hi

ch2 blue is the 11 feet clk of 273, ch4 green is the 2 feet of 273,
Q: Can ch2's 11 pin rising edge parameters such as oscilloscope, picture, 0.5v trigger the output of 273

The maximum V_IL is guaranteed to be at least 0.8 V.

But where exactly did you measure the CLK signal? I would guess that the spike is larger directly at the pin. (And with the new die being faster, a short spike wold be fast enough to trigger the flip-flop.)

Hi

The (clk) level of the measured device is a little out of specification,

HI

Channel 2 is the signal of clk, channel 2 is the direct measurement of clk PIN11 pin, from the oscilloscope measurement results, the width of time may be consistent, but the level is indeed triggered at 0.5V.