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74LVCH244A simulation model and bus hold question?

Other Parts Discussed in Thread: SN74LS244

Is there a simulation model available for this device?  I'm using TINA and implementing SN74LS244's and having the input either be a GND or a float.  When the input is grounded I want the output of the 2nd buffer (VF1) to be GND since the load is being pulled up to 3.3V via a 4.7K resistor. When the input is float, I want the input to be pulled up, so that my output VF1 is 3.3V, hence no current though the load.  I see that the SN74LS244 don't have bus hold, so a pull up on the input would resolve this, however on the 74LVCH244A, if the input is disconnected (floating) as opposed to grounded, will the input be pulled to 3.3V?  Could I add a pull resistor on the input anyway?

 

Technically the way it's set up is Buffer 1 (IN)  -->  FPGA --> Buffer 2 (OUT) --> LOAD, so the FPGA acts like a buffer too.

testinput.TSC