SN74LV123A: Upper and lower limit for pulse width

Hiromu Susami

Prodigy 70 points

Part Number: SN74LV123A

Tool/software:

Hi experts,

The output pulse width t_w is determined by the following equation:

t_w = K × R_T × C_T

Is there an upper and lower limit for pulse width t_w that can be set?
(For example, is it OK to set t_w=60s?)

In addition, are there upper and lower limits for resistor R_T and capacitor capacitance C_T in this device? As for the upper limit, I thought that if there were no problems with the size of the capacitors and resistors, the pulse width could be as large as possible, but what about that?

1 day ago

+1 Clemens Ladisch 1 day ago

Guru 260500 points

The graphs in section 10.2.3 show the typical values that you are expected to use.

For very small C and R values, the capacitance/resistance of the traces and the chip itself become noticeable. For very large C and R values, the leakage current of the capacitor might become noticeable; this depends very much on what capacitor you're using.

0 Hiromu Susami 1 day ago in reply to Clemens Ladisch

TI__Prodigy 70 points

Thank you for your answer.
Intuitively, is it realistic to set t_w=60s?

+1 Clemens Ladisch 23 hours ago in reply to Hiromu Susami

Guru 260500 points

You would need a very large capacitor. Check its datasheet; its worst-case leakage current must be much smaller than the current through the resistor. An electrolytic capacitor probably will not work.

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SN74LV123A: Upper and lower limit for pulse width