• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 21 subscribers
  • Views 442 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74GTL2003: IC function check

Boyan Lu
Expert 7005 points
Part Number: SN74GTL2003
Other Parts Discussed in Thread: LSF0108

Tool/software:

Hi Team

My customer would like to consult with you and discuss the internal MOS action principle of SN74GTL2003. The picture below is the internal circuit of SN74GTL2003. From the picture, it shows the current wiring method and action. However, the customer is very curious that from the action point of view, N-MOS VGS If it is turned on, VDS will also be turned on. Logically speaking, D1 will also be 1.8V. Why is the potential of D1 3.3V?

Thanks,

Boyan

  • 0
    TI__Mastermind 40046 points

    Hi Boyan,

    This set of logic minute videos should help clear up the functionality of the internal FETs: https://www.ti.com/video/series/understanding-the-lsf-family-of-bidirectional--multi-voltage-lev.html (both the GTL2003 and LSF0108 share similar architecture for level shifting). 

    Please specify further if still unclear.

    Thanks,

    Jack 

  • 0
    Prodigy 20 points

    Hi Jack,

    Thanks for your sharing video of level shift introduction. After watched this video, i still don't know detail action principle of the internal FET because it only introduce simple action for level shift IC.  As Boyan mention to show internal logic circuit, I hpoe TI share more relation introduction of internal logic circuit, and then step by step. 

    Jeff

  • 0
    Guru 316640 points

    The current flowing into DREF and out of SREF is limited by the resistor. Therefore, GREF is just at the threshold voltage, i.e., only such a small current can flow.

    When D1 is an input, then the RDS of the FET is so large that S1 cannot go above 1.8 V. (A pull-up at S1 makes the output voltage more robust.)
    When S1 is an input, then the RDS of the FET is so large that the voltage at D1 is determined by the pull-up resistor.

  • 0 in reply to Clemens Ladisch
    Prodigy 20 points

    Hi Clement,

    Thanks for your detail explain of what is my real question. So the FET of level shift design is abnormal specifcation with large RDS, right? When S1 is an input and voltage level convert to low and DI pull high 1kohm , has probability that D1 can't convert to low?

  • 0 in reply to jeff pan
    Guru 316640 points

    I do not understand what you mean with "abnormal".

    When S1 is an input with a low logic signal, then the gate-to-source voltage is large enough for RDS to be very low. The device that pulls S1 low will also sink the current through the 1 kΩ pull-up.