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TPLD1201: logic-Gate with 4 inputs

Egon Hirsch
Expert 3550 points
Part Number: TPLD1201

Tool/software:

Hello all,

my customer wants to program our TPLD1201. He wants to use a logic gate with 4 inputs. With 4 tomes zero 0000 he wants to achieve on the output 1.

But on the simulation the customer gets a different result:

What is the reason for this? Attached the programming file:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/151/statemachine_5F00_TI_5F00_Anfrage13082024.syscfg

Best regards

Olaf

  • 0
    TI__Genius 12841 points

    Hi Olaf,

    Thanks for bringing this to my attention I am looking into this now.

    This is highly concerning, and I can give you a  better answer tomorrow.

    -Owen

  • 0
    TI__Mastermind 25670 points

    Hi Olaf,

    I investigated your file. This issue is being caused by the RST pin for "in.timer" being connected to both the input and output pins of "PWM". This is causing some sort of feedback loop within the SPICE engine that is breaking everything. You will see if you disconnect the RST pin that the simulation will proceed to work as expected.

    For a quick fix on your end without changing functionality (just for simulation purposes), you can buffer the output of "PWM" with an AND gate as I've shown in the picture below. I have also highlighted the problematic signal path for you. Please let me know if you have any further questions.

    Best,

    Malcolm