SN74LVC2G74-Q1: 500V HBM ESD test

Amber Si

Part Number: SN74LVC2G74-Q1
Other Parts Discussed in Thread: SN74HCS74-Q1

Tool/software:

Hi team,

Do you know if we have output Q level flip issue when 500V HBM ESD test in PRE/CLK/Q pin? my customer found this issue and want to know why.

Amber

1 month ago

0 Albert Xu1 1 month ago

TI__Mastermind 24055 points

Hi Amber,

Can you expand a bit more on what the issue is? As of now there are no known issues with the device.

0 Clemens Ladisch 1 month ago

Guru 272280 points

High-impedance CMOS inputs can be easily switched by an ESD event. If you want to make them resistant to that, then you have to add a filter that can absorb all the ESD energy.

0 Amber Si 1 month ago in reply to Clemens Ladisch

TI__Intellectual 1380 points

Yes Clemens，you are right， so do we have filter component design reference for customer?

0 Clemens Ladisch 1 month ago in reply to Amber Si

Guru 272280 points

In general, ESD is not the primary problem for signal inputs.

When the signal comes from a user-accessible, mechanical switch, then you need debouncing, and that is enough to also protect against ESD. Due to the resulting slow edges, you usually need Schmitt-trigger inputs. See the SN74HCS74-Q1 datasheet for an example application.
When ESD is a possibility because the signal input is hot(un)plugged, then ESD cannot happen during normal operation, and clamping diodes are enough.
When the signal input cannot be touched, then ESD is not a problem.

So why did the customer choose to do an ESD test directly on the PRE/CLK inputs?

0 Amber Si 1 month ago in reply to Clemens Ladisch

TI__Intellectual 1380 points

Hi Clemens,

Customer want to evaluate pin ESD resistibility.

0 Albert Xu1 1 month ago in reply to Amber Si

TI__Mastermind 24055 points

Hi Amber,

This device is rated for 2kV HBM. Can you go a bit more indepth on what the issue you are seeing?

Logic

Logic forum

SN74LVC2G74-Q1: 500V HBM ESD test