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TXS0108E: sleep mode work abnormal

Part Number: TXS0108E

Tool/software:

At present, our low-power doorbell products use TXS0108E (connected to WiFi module and main control SOC, communicating through SDIO, and the level shift enable pin OE pin controlled by low-power MCU). However, when encountering SDIO on the 1.8V side of the conversion chip (Wi Fi module) in sleep mode, there is a voltage of about 0.42V, which has not fully entered the high impedance state.

WiFi module manufacturers have separate cables that fly out of the module, and after the device enters sleep mode, they sequentially disconnect the connections on the SDIO BUS. Each disconnection reduces the power consumption of VDDIO, and after all are disconnected, the power consumption of VDDIO is around 80uA (the normal static current of WiFi modules). Module manufacturers speculate that the leakage is mainly caused by SDIO (consumption of level conversion chips).

For OE timing, the following experiments were conducted synchronously:
1. The OE pin of the MCU control level shift is pulled down 200ms in advance before SOC power failure. After entering sleep mode, the VDDIO current of the WiFi module will have jagged edges;

2. The MCU controls the level shift OE pin to power off the SOC for about 5 seconds, and then lowers the OE to enter sleep mode. After entering sleep mode, the VDDIO of the WiFi module has no jagged edges. But during the period when SOC starts to power down and OE is pulled low, the level is not completely pulled down.

From the results, it can be seen that the level shift OE pin will power down after the SOC, and the power consumption of the VDDIO module will be relatively low in this situation. However, WiFi module manufacturers do not recommend using this timing requirement.

In summary, please arrange to consult with TI's original factory to confirm the specific cause and solution for the leakage of the conversion chip.

  • When OE is high, all I/O pins have internal pull-up resistors. When OE is low, all I/O pins are floating.

    Please specify exactly what voltages you expect at the I/O pins, and what you actually measure.

  • Hi Sam,

    In addition to Clemens questions, what is the minimum timing requirement between MCU shutting down and OE driven low? Have we tested for this case to find a compromise between the OE timing and VCCB ramp down time with less leakage? 
    Regards,

    Jack