TXV0106: DP83867IR with TXV0106 Timing Budget

Hi Tom,

The TXV 0.3 ns example is skew from the output of the device and not in addition to skew from other peripherals connected to the device.

For example, MAC's skew of < 1 ns into the TXV device as input will translate into an output skew of 0.3 ns total output skew into the peripheral connected to the outputs of the TXV device, thanks.

Best Regards,

Michael.

Hi Michael,

how would an asynchronous driver do that? Could you please point me to that feature documented in the datasheet?

Thank you very mouch.

Greetings

Tom

Hi Tom,

It is not a feature, but a specification, i.e. the device was characterized and specified for the output skew documented in the data sheet.

This guarantees skew between the output of the TXV device. For example, figure 3-1 of Overcoming Design Challenges - Implementing High Performance Interfaces shows 21 ps skew between outputs of the device with input driver skew < 2.6 ns, within RGMII's requirement in the below table.

If I understand correctly, your system looks like MAC -> TXV -> DP83867? If so, note that RGMII's requirement shown below is for 500 ps skew which is below TXV's spec. Hence, how much TXV skew would meet your requirement?  Thanks.

Best Regards,

Michael.

Hi Michael,

thank you very mouch for your reply.

You understood me correct, my system looks like MAC -> TXV -> DP83867 and vice versa.

But I still have some troubles to follow:

"The TXV 0.3 ns example is skew from the output of the device and not in addition to skew from other peripherals connected to the device. For example, MAC's skew of < 1 ns into the TXV device as input will translate into an output skew of 0.3 ns total output skew into the peripheral connected to the outputs of the TXV device[..]"

I interprete this as that the TXV0106 can somehow reduce skew <1ns at its input to < 0.3ns at it's output. But the TXV0106 has no clocked register, so I doubt that you meant that.

The equations I wrote for setup and hold times come from this TI application Note for DP83867: RGMII Interface Timing Budgets We can use the RGMII v2.0 Specification values of 1.2ns setup and hold time for TX-path (MAC to PHY via TXV) for further discussions instead, they are not my primary concern.

My concern is that to meet those timings at the PHY, a MAC has now, with the TXV and its skew of 0.3ns, only 2ns -1.2ns -0.3ns = 0.5ns allowed skew at its TX-Port. To me, seems not practical for any fpga to meet. Do you know systems wher this kind of case (fpga -> txv -> phy) works?

Thank you, Tom.

Hi Tom,

I see, and you are right as that is not what I meant. I meant the input skew of the TXV is based on the MAC's output skew while the TXV output's skew is as specified based on the data sheet's conditions. 

We also do not specify setup and hold times for TXV and have further gone ahead to move the thread to the PHY team for additional clarifications as I presume they would have more experience with systems as such, thanks.

Best Regards,

Michael.

Hello,

I will be assisting from the PHY team. Can you please summarize what the concern is?

Regarding RGMII, all that the PHY cares about is that setup and hold time are met at the pins (if input in the specific mode, shift or align).

Sincerely,

Gerome