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SN74LVC1G17: Is it possible to use Behavioral SPICE Model for analog simulation (Simetrix)

Part Number: SN74LVC1G17

Tool/software:

Dear Specialists,

My customer is considering SN74LVC1G17 and has a question about Behavioral SPICE Model.

I would be grateful if you could advise.

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I would like to confirm whether the Behavioral SPICE Model of SN74LVC1G17 provided by HP can be used for analog simulation.

Can this simulation model confirm the rise time, fall time, and input-output delay for analog input signals?

Simulation software is Simetrix.

www.ti.com/.../scem635

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I appreciate your great help in advance.

Best regards,

Shinichi

  • Hi Owen,

    Thank you for your answer.

    Shinichi

  • Hi Owen,

    The customer has additional questions.

    Could you please advise?

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    Regarding the SPICE Behavior Model for SN74LVC1G17,

    -Does it include characteristics of rise time, fall time, and propagation delay time?

    -Does it include characteristics of parasitic capacitance such as input parasitic capacitance and output parasitic capacitance?

    -In what ways is the IBIS model superior to the SPICE Behavior Model for checking timing characteristics?

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    I appreciate your great help and cooperation.

    Best regards,

    Shinichi

  • Hi Shinichi,

    The SPICE model does not include characteristics for rise/fall, and for propagation delay it contains an idealized version where it is just based strictly off typical values at certain voltages. It's input and output parasitics while included are also idealized and may not accurately reflect the ones observed on the chip/per package.

    The SPICE model is meant to be behavioral. Used to prove that logic is correct before going into deeper analysis and testing of the circuit.  

    The IBIS model is generated off design data giving accurate estimates for parasitics across packages, across temperatures, and across voltages. It can give better results when checking parameters like Rise/fall time as those have to be done with nanosecond accuracy, and can be verified at the conditions expected of the final project.

    Regards,

    Owen