Hello.
I am currently using the TXB0108PWR part for 2.5V to 3.3V level conversion on one of my boards. An FPGA located close to the chip drives the 2.5V VCCA side. The 3.3V VCCB side drives some signals on another PCB, connected via a shielded flat-flex cable (FFC). I'm having some trouble sending a 50MHz clock through this cable. The load is a 1:8 clock distribution/driver chip located on the 2nd PCB.
The FFC is 51 conductor, 0.5mm pitch, like this one found on Digikey. http://search.digikey.com/us/en/products/PS564-AB-0051-S/PS564AB0051S-ND/705643 The conductor dimensions are about 11mil wide by 3mil thick. There is an outer layer of shielding on each cable, which is grounded to the outside traces/pins (1 & 51). I'm not sure what the capacitance or impedance of the cable is. The odd traces carry various signals. The even traces are all ground, for closely coupling the return currents.
The TXB0108PWR chip is powered by 2.5V on VCCA and 3.3V on VCCB. Each power pin has a .1uF bypass capacitor located near the pins. Each of the VCCB side signal pins have a 0 ohm resistor in series for termination purposes. I haven't tried changing these values much yet.
The circuit works with a shorter UNshielded FFC that is about 12" long. When I try using a 13" shielded FFC edges are lost. I see about a 16MHz clock instead of a 50MHz one.
I've come to realize that this level converter chip has a pretty limited current drive capability, and may not be well suited for driving such a capacitive load. Further, I'm worried that reflections on the VCCB side may be activating the internal one-shot and floating the VCCB side prematurely (the reflection appears as if a master on the second board is attempting to drive the bus). Is that possible?
In the future, I would like the circuit to work using a cable length of up to 550mm (21"). Are there any options besides differential signaling? That would double my pin budget.
Thank you for your advice.