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TWL1200 AUDIO_CLK maximum frequency.

Alex Milgrom
Prodigy 40 points
Other Parts Discussed in Thread: TWL1200

Hi All.

We're considering the usage of the TWL1200 level shifter to connect a WiLink6.0 based WIFI+BT combo solution (with 1.8V I/O) to a host SoC that operates @ 3.3V levels.

WiLink6.0 requires a reference clock input, one of the WiLink6.0 supported reference clock options is a digital, 1.8V referenced 26MHz clock.

Our system can provide only a 3.3V referenced 26MHz digital clock. This means that we need to "down-shift" the 3.3V 26MHz clock to 1.8V voltage levels.

Since we intend to use TWL1200 level-shifter for SDIO and UART translation, and we do not plan to use the AUDIO interface of WiLink6.0, the AUDIO part of TWL1200 remains unused.

What I've had in mind is to use the AUDIO_CLK translation terminals of TWL1200 for our 3.3V 26MHz clock translation to 1.8V, My question is whether this is possible? I could not find maximum data rates for the AUDIO section of TWL1200 in the TWL1200 datasheet.

Thanks.

Alex M.

  • 0
    TI__Genius 9085 points

    Most of our standard buffer type translators should have no problem with this, so my assumption is that it will be fine. I will double check with design and let you know.  

  • 0 in reply to Hattie
    TI__Genius 9085 points

    The signal looks good. This was done with a 15pF load.

     


  • 0 in reply to Hattie
    Prodigy 40 points

    Thanks Hattie.

    I suspect that the image attached to your answer is the output of a simulation software (using the IBIS model?), am I correct?

    Could you give the additional parameters (such as TWL1200 VCCA and VCCB voltages, 3.3V clock source drive strength and trace capacitance etc..) used in this simulation?

    Thanks.

    Alex M.

  • 0 in reply to Alex Milgrom
    TI__Genius 9085 points

    This simulation was run by our design team using the design files.

    Input was 3.3V (VCCA), output was 1.8V(VCCB). The trace/load capacitance was 15pF. There was also a 1MOhm resistor to GND on the output. 

    I will have to double check on input drive strength used in simulation. It was likely a standard simulation voltage source. Since this single direction buffer has a high impedance input, standard driver configurations will have no problem. If you are concerned about the driver being weak, we can run additional simulations with a given spec.