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Original question:

Daisey-chaining shift registers.

SN74HC595: TLC59283 >> Shift register clock and data misalignment

Salvatore Battiato
Prodigy 10 points
Part Number: SN74HC595
Other Parts Discussed in Thread: TLC59283

Tool/software:

Hello everyone! New to the forum here. Sorry if the part is wrong but apparently I can only choose power managment subforum with this IC.

I'm designing a led driver with TLC59283. Because of led number in the design I'd like to max out the SPI interface driving multiple TLC59283, at 32MHz.
My concern is about the clock and data synchronization using one shared clock and multiple shift registers daisy chained. According to the TI datasheet, the typical propagation delay is rated at 11ns and the max delay at 20ns. Now, from what I know, since the clock period is T=31.25ns,

  • If the delay is < 7.8125ns (T/4), clock and dout are not perfectly in sync, but I can resync the two signals with a cheap D flip flop and one NOT gate after the original clock to feed rising edges to the next shift register
  • If the delay is > 7.8125ns (T/4), clock and dout are completely out of sync, so the only way to make them readable again is by delaying the clock precisely to match the propagation delay. This route is expensive, and hard to implement, since I don't know the exact propagation delay of each shift register. 


Am I obliged to make the circuit work at 10MHz to stay safe behind the max 20ns delay?

  • 0
    Guru 316640 points

    The propagation delay does not matter. The SOUT→SIN connection between two chips is exactly the same as the connection between the flip-flops inside the chips. Just chain the chips together, and use the same clock signal for all of them.

    The only thing you need to care about is the delay of a long SCLK line. As mentioned in the linked question, routing the SCLK trace from the master to the last shift register and from there back to the first shift register ensures that any clock delays will not affect the data propagation.

    The maximum frequency depends on the total clock delay. If the clock line is so long that you need to insert buffers, then it will not possible to reach 32 MHz.