Part Number: TPLD1202
Tool/software:
Hello,
I have done the following simple design in the Interconnect studio tool:
My watchdog configuration is the following:
However, the simulated behavior is totally erratic, the resulting triggering delay and pulse width are way out of expectations.
Configured as 25MHz/64 for the watchdog clock, I wouldn't expect with my configuration a watchdog triggering of 608µs and a pulse width of 181µs as depicted on the following curves:
Am I missing something or is this a bug ?
I have attached the design file if needed.
Clément
