Other Parts Discussed in Thread: SN74LVC1G07, SN74HCS165
Tool/software:
To whom it may concern,
I am the SI engineer of Oracle Hardware Development team. For our X12-2C design, we are having SN74LV165APWR shift registers for the power good signals. The falling edge of the signals are mostly between 250ns and 540ns. But there are two signals that are 1.4ms. I was reading the datasheet but cannot find the fall time spec on the spreadsheet. Please advise if these numbers are OK.
We are also having the powerok signals that has rise time varies from 83ns to 212ns on SN74LVC1G07. Similary, I cannot find the rise time requirement for SN74LVC1G07 as well. Please help advise if the rise time is OK for the IC.
Thanks,
Xin
