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TPLD-ICS: The problem of pulse width output by edge detector

m l
Prodigy 60 points
Part Number: TPLD-ICS
Other Parts Discussed in Thread: TPLD1202

Tool/software:

Hi,

When using edge detection logic devices, I found that the pulse width output when the corresponding edge is detected is 230ns, which is a bit too long for my current design requirements. I want to know how to reduce the width of this pulse.

thanks！

  • 0
    TI__Expert 4481 points

    Hello,

    Just to clarify, are you using the TPLD1202 and is this the edge detector block? If so, the simulation tool is not exact on the length of the pulse width that is output by the edge detector. The real pulse width would be approximately 20 ns.

    Best,

    Ian

  • 0 in reply to Ian Graham
    Prodigy 60 points

    Hi,lan Graham.

    Yes, I am using the edge detector block of TPLD1202. I understand that you mean the pulse width output in actual testing is 20ns, and this size cannot be changed.

    thanks！

  • 0 in reply to m l
    Prodigy 60 points

    Hi,Ian Graham.

    When I was still using the delay block, I found that once the delay time exceeded the high-level time of the input signal, the output waveform became abnormal.

    This is a waveform with normal delay：

    This is an abnormally delayed waveform：

    thanks！

  • 0 in reply to m l
    TI__Expert 4481 points

    Hi, this is normal for this type of delay block and does reflect the performance of the actual device. From the datasheet: 

    For delay applications, it is recommended to use larger counter data values for less error. If an input pulse width is shorter than the specified delay time, the pulse will be filtered out. This feature can be useful for deglitching.

    Best,

    Ian