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TPLD-ICS: The problem of pulse width output by edge detector

m l
Prodigy 90 points
Part Number: TPLD-ICS
Other Parts Discussed in Thread: TPLD1202

Tool/software:

Hi,

When using edge detection logic devices, I found that the pulse width output when the corresponding edge is detected is 230ns, which is a bit too long for my current design requirements. I want to know how to reduce the width of this pulse.

thanks！

  • 0
    TI__Genius 9851 points

    Hello,

    Just to clarify, are you using the TPLD1202 and is this the edge detector block? If so, the simulation tool is not exact on the length of the pulse width that is output by the edge detector. The real pulse width would be approximately 20 ns.

    Best,

    Ian

  • 0 in reply to Ian Graham
    Prodigy 90 points

    Hi,lan Graham.

    Yes, I am using the edge detector block of TPLD1202. I understand that you mean the pulse width output in actual testing is 20ns, and this size cannot be changed.

    thanks！

  • 0 in reply to m l
    Prodigy 90 points

    Hi,Ian Graham.

    When I was still using the delay block, I found that once the delay time exceeded the high-level time of the input signal, the output waveform became abnormal.

    This is a waveform with normal delay：

    This is an abnormally delayed waveform：

    thanks！

  • 0 in reply to m l
    TI__Genius 9851 points

    Hi, this is normal for this type of delay block and does reflect the performance of the actual device. From the datasheet: 

    For delay applications, it is recommended to use larger counter data values for less error. If an input pulse width is shorter than the specified delay time, the pulse will be filtered out. This feature can be useful for deglitching.

    Best,

    Ian

  • 0 in reply to Ian Graham
    Prodigy 90 points

    Hi,Ian Graham.

    Okay, I understand what you mean. As for the two questions mentioned above, I have one more question to add. Can the pulse triggered by edge detection only be 20ns? Can this value be modified? Can the function of clearing when the pulse width is lower than the delay time be turned off?

    thanks!

  • +1 in reply to m l
    TI__Genius 9851 points

    Hi,

    The edge detection pulse from the edge detector block is always 20 ns. The delay block filtering out short signals can not be turned off. You can build a delay block using the logic and timing elements in the TPLD, as I've done below, but delaying a signal with this method still filters out pulses received while the first pulse is being delayed, shown in the simulation.

    Best,

    Ian

  • 0 in reply to Ian Graham
    Prodigy 90 points

    Hi,Ian Graham

    Can you provide me with the specific configuration diagram for each block?

    Thanks!

  • 0 in reply to m l
    Prodigy 90 points

    Hi,Ian Graham

    It's okay, I have implemented a delay beyond the high level time of the input signal through your logic diagram. Thank you for your help.

    Thanks!

  • 0 in reply to Ian Graham
    Prodigy 90 points

    Hi,Ian Graham

    If I want to use other logic devices to achieve delay, then my overall logic resources will not be enough. I would like to ask if there is any way to use delay blocks to achieve delay operations with a delay time higher than the high-level time of the input signal.

    Thanks!

  • +1 in reply to m l
    TI__Genius 9851 points

    Hi,

    No, there is not a way to implement the delay with only delay blocks. If you send me your design or tell me what blocks you aren't using, I can try to design a delay circuit with what you have left over.

    Best,

    Ian

  • 0 in reply to Ian Graham
    Prodigy 90 points

    Hi,Ian Graham

    I have resolved the issue of insufficient resources. Thank you very much for your reply.

    Thanks!