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UCC28070: UCC28070 for DC Input PFC Application

Conor
Guru 10210 points
Part Number: UCC28070

Tool/software:

Hi,

I am reaching out to inquire about the feasibility of using the UCC28070 in a DC input power supply application with a PFC configuration. While we understand that the IC is primarily designed for AC input applications, we have implemented it in a DC input system to function as a boost converter. Initial testing indicates that the circuit operates as expected, but we would like to confirm whether this use case aligns with the theoretical capabilities of the IC.

Current Understanding and Observations

  1. Continuous Conduction Mode (CCM) Operation:
    We believe that the UCC28070, designed for CCM, does not rely on AC signal detection, making it suitable for DC input operation.

  2. Interleaved Configuration:
    Due to the high peak current in our application, we opted for an interleaved configuration to distribute the current and improve system efficiency. This approach has shown benefits in reducing the size and cost of components like inductors and switching elements.

  3. Use Case Description:

    • The application involves a low-voltage, high-current DC input.
    • To avoid the need for large, high-current-rated components on the primary side, we boost the input voltage immediately using the UCC28070.
    • Harmonic correction is not a priority; the focus is solely on boosting the voltage efficiently.

Questions for Your Consideration

  1. Are there any theoretical or practical limitations to using the UCC28070 in this manner?
  2. Could any of the built-in features, such as UVLO or OVP, cause potential issues in a DC input scenario?
  3. Are there specific design considerations or precautions we should take to ensure reliable operation in this context?

Thank you for your time and support. I look forward to your response.

Best regards,

Cornor

  • +1
    TI__Mastermind 33970 points

    Hello Conor, 

    The UCC28070 controller has been used successfully with DC input by other customers, although the design procedure to do this is not well documented.

    There are several design issues to consider and limitations to overcome or accommodate. 

    The first is that the UCC28070 implements "quantized feed-forward" compensation for the voltage-loop control and relies on AC peak detection (through VINAC input) to determine the RMS input voltage.  To capture a peak voltage, the circuit must determine when a half-cycle is over, so the AC zero-crossing is considered to be detected when VINAC drops below 0.7V.   A change in peak voltage in a new half-cycle over a previous half-cycle can be immediately detected, but a fall from a higher peak to a lower peak cannot be detected without the zero-crossing to indicate the end of a half-cycle. 

    By default, the UCC28070 multiplier gain coefficient kVff always starts at the highest level for the lowest gain (to avoid starting with excessive gain at high line) and relies on zero-crossings to detect lower peak AC and change to appropriate gain corresponding to the correct RMS input level.

    With a DC input, there are no zero-crossings, so falling changes in DC input amplitude cannot be detected unless a periodic "artificial zero-crossing" (AZC) is implemented at the VINAC input.  Such an AZC circuit must replicate certain signal attributes to mimic an AC zero-crossing, which includes certain maximum dv/dt and dwell time below 0.7V.
    Specifically, the falling and rising dv/dt of VINAC must be <1V/30us (estimate) and VINAC must dwell below 0.7V for at least 50us.  

    Another aspect of the kVFF scheme is that loop gain is adjusted based on the assumption of RMS voltage = peak voltage/1.4142.  For DC input, this assumption is not valid, and RMS values are underestimated by a factor of 1.4142.   So the VINAC divider ratio can be adjusted to result in Vrms = Vdc for the proper gain level, or the IMO resistor can be adjusted to restore the 1.4142 factor for output power. 

    Since THDi has no meaning with a DC input, the divider-ratio of VINAC does not need to equal the divider-ratio for VSENSE and accurate reproduction of the inductor current down-slope is not necessary. 

    The UCC28070 does not incorporate input UVLO or input OVP, so there are no considerations for these features. 

    The kVFF gain levels are optimized for the "universal" AC-line range of 85Vac to 265Vac.  That represents a 3.12:1 range of RMS voltage.  If the DC input range exceeds this range, further changes in multiplier gain (by kVFF factors) cannot happen, so either a current limit will be triggered at the low-voltage end, or excess power may be possible at the high-voltage end. 

    Regards,
    Ulrich