• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 20 subscribers
  • Views 399 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74AXC1T45: SN74AXC1T45

Rahul M
Prodigy 20 points
Part Number: SN74AXC1T45
Other Parts Discussed in Thread: SN74AUC1G17, LMK00804B

Tool/software:

Hi , i have clock being generated from my FPGA for the DUT. The FPGA generates a 2.5V (LVCMOS) @ 320MHz , i need to voltage translate it to 1.2V ( LVCMOS ) @ 320MHz for the DUT.
Can SN74AXC1T45 be suitable for this application ?

In the data sheet it says 500Mbps when translating from 1.8V to 3.3V.
So what is the rate when translating from 2.5V to 1.2V.

Thanks.

  • 0
    Guru 317280 points

    A safe estimate, based on the propagation delay of 7 ns, is 143 Mbps = 71 MHz.

    The fastest device at 1.2 V is the SN74AUC1G17, which can do more than 256 Mbps = 128 MHz.

    A 320 MHz clock should be transmitted not with a logic signal but with LVDS.

  • 0 in reply to Clemens Ladisch
    Prodigy 20 points

    My FPGA can generate a LVDS clock (LVDS_2.5V STD ) so i will use a LVDS receiver at my DUT that convert LVDS (2.5V STD ) to LVCMOS ( 1.2V ), will that do work for me ?

    If yes can you please suggest a LVDS receiver that will convert to LVCMOS (1.2v) as well as support my data rate ( 640Mbps / 320MHz )

  • 0 in reply to Rahul M
    Guru 317280 points

    There is no LVDS receiver (or any other device) that can generate a 320 MHz signal at 1.2 V.

    In the ideal case, the DUT would support LVDS. What exactly is that DUT?

  • 0 in reply to Clemens Ladisch
    Prodigy 20 points

    We have an ASIC Chip ( The DUT ) , which needs to be evaluated.
    We have designed a PCB and we are trying to generate all the necessary signals from the FPGA ( A Zed Board in our case )
    The DUT requires a Master Clock @ 320Mhz (1.2V LVCMOS ). we wanted to put a clock buffer on the PCB but we are unable to find a match for our specs.

    The DUT was designed to handle only LVCMOS @ 1.2V. 

    PS: The FPGA (zed board) can generate 
    1. LVDS 2.5V STD
    2. LVCMOS ( 1.8V or 2.5V)

  • +1 in reply to Rahul M
    Guru 317280 points

    Again, there is no device that can generate a 320 MHz signal at 1.2 V. The clock buffer with with the lowest output voltage is the LMK00804B, supporting 1.5 V (it requires a 3.3 V core supply, and note that it prefers a differential input).

    You could try to use the LMK00804B; your DUT is likely to work with an input signal that is 0.3 V too high.

    You should redesign your ASIC to support LVDS inputs.