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CD74HC4046A: Phase-frequency detector (PFD) noise performance

József Hermann
Expert 1040 points
Part Number: CD74HC4046A

Tool/software:

Dear Forum,

I would like to ask wheter PC2 comparator hf CD74HC4046A is dead-zone free?

PC2 has a tree-state voltage output and goes to Hi-Z state when PLL reach locked condition (phase difference is 0 deg, after small correnting pulses generated, the best is if correcting pulses can be

very small too (~less then tpd of a logic gate), ensuring constant senstivity along the entire tuning range without abrupt).

74HCT9046A (no longer produced) exhibits a 'no-dead zone' feature achieved by combination of current output and a technique that internal 'Up' and 'Down' source/sink simulataneosly conducts for a short time.

Is it possible the CD74HC4046 has similar feature (anti-backlash time ->internal D flip-flops async reset is delayed ~10..15ns) despite it is a voltage out device (however, FET current limit ~ current generator)? Because TI document SCAA088 uses the PC2 of 4046A for low phase noise requirement.

Regards,

Joseph

  • 0
    TI__Genius 12380 points

    Hi Joseph, 

    CD74HC4046 does not have this feature to eliminate the dead-zone, and as a result the close-in phase noise can be degraded in some applications. The PC2 output can only operate as "source", "sink", or "high impedance". In the application note you mentioned, the performance impact of the dead-zone is minimized by using such a low frequency for the phase detector (44.1kHz phase detector frequency compared to a dead-zone in the range of 10s of ns). Let me know if this answers your questions. 

    Regards, 

    Connor 

  • 0 in reply to Connor Lewis
    Expert 1040 points

    Hi Connor,

    thanks for your answer! It is useful for me: if the PFD reference signal periode time much larger than internal gate tpd ~15ns the noise degradation effect of correcting spikes can be neglected. In my case the fref would be max 10 KHz, however "N" is quite large (~1000). Low fref predicts small loop filter time constant(s) as well which also effectively supresses VCO unwanted modulation. Higher frequency pole can also be added to the basic loop 1st order loop filter to even improve higher frequency attenuation (~spikes). Of course this added pole shall be enough high frequency allowing the PLL loop treated still as standard 2nd order system. Your SWRA029 and SLAA011b also very useful references.


    Regards,

    Joseph