• State TI Thinks Resolved
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 19 subscribers
  • Views 53 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

SN74LVC1G10: Design schematic

Maria Senyer
Prodigy 40 points
Part Number: SN74LVC1G10

Tool/software:

Dear Technical Support Team,

I am desgnin a reset circuit for my microcontroller with your product SN74LVC1G10DCKR.

What I am intending to do is, when the three buttons pressed in the device, a reset is performed to the microcontroller.

These are the connections of the membrane keypad:

BTN_EXT is not currently used.

This are the connections to the SN74LVC1G10DCKR chip and the microcontroller:

Appart from taking into consideration the pull-downs for the membrane keypad, and considering that VBAT will never go anywhere under 3.0 V, is there any other consideration I am missing for the design?

Any other capacitors, or extra design stuff that I need to take into account for this to work?

Thank you.

  • 0
    Guru 298810 points

    The NAND gate's output is connected directly to the R-C reset circuit. So when the gate powers up, it will override the reset pulse. Futhermore, the output might be overloaded because of the large capacitor.

    Insert a diode implement a wired AND, and a resistor to limit the current.

  • 0 in reply to Clemens Ladisch
    Prodigy 40 points

    Dear Clemens Ladisch,

    Thank you for your answer and sorry for my little knowledge in this area.

    I partly understood what you said, but I still have a few questions:

    Clemens Ladisch said:
    So when the gate powers up, it will override the reset pulse

    I understand that here you mean that, the R-C reset circuit should provide a reset at the beggining of the power-up sequence of the device, so performing a reset to the microcontroller. Because the output of the reset is directly connected to that R-C reset circuit, the RST signal may force a '1' in that pin, so never performing a reset on the microcontroller, is that correct?

    Clemens Ladisch said:
    Futhermore, the output might be overloaded because of the large capacitor.

    This, I don't understand. Could you explain it please?

    Clemens Ladisch said:
    Insert a diode implement a wired AND

    Here, are you suggesting I place a diode like this?:

    Clemens Ladisch said:
    and a resistor to limit the current.

    Here I am a bit lost, where should I put the resistor? Before the diode?

    Thank you.

  • 0 in reply to Maria Senyer
    Guru 298810 points

    You want to pull down the reset signal, but not up. So the diode must go in the opposite direction.

    A capacitor acts like a short. The absolute maximum for the output current is 50 mA; more can damage the gate. Taking the diode's forward voltage into account, you need a series resistor of at least (3.3 V − 0.6 V) / 50 mA = 54 Ω; use 100 Ω to be safe.

  • 0 in reply to Clemens Ladisch
    Prodigy 40 points

    Hello,

    Okay, I will place the dioe in the opposite direction.

    I still don't understand (sorry for my unexperience) where should the resistor be placed. From your answer I understand it needs to be next to the diode: like this maybe?

    Thank you

  • 0 in reply to Maria Senyer
    Guru 298810 points

    Yes, somewhere in series like this.

  • 0 in reply to Clemens Ladisch
    Prodigy 40 points

    Okay, thank you Clemens, you've really helped me a lot.

    I will try to test this in LTSpice and then in my circuit.