TXS0108E-Q1: SDIO Level Shifting Clock drooping during Operation

Hi 

I have decoupling capacitors next to pins 2, 19- just missing from the schematic

I have measured both 3.3V & 1.8V on the decoupling capacitors- no voltage drop was measured over them

Hi Mata,

In addition to Clemens' suggestion, is suggested to have external pullups removed as the device has internal pullups already. Are there any pullups/pulldowns not shown in this schematic? 

Regards,

Jack

Hi Jack,

There are no pull-up or pull-down resistors on either side of the level shifter across all 6 signals (CLK, CMD, DATA).
Also, the series resistors are 0 ohm.

Another question:
As you can see in the picture below, the CMD_1.8V line is idle at 1.8V. However, when communication starts, it doesn't manage to reach 1.8V.
Do you have any idea why?

Hi,
I’ve reviewed the SDIO signals using an 8-channel scope and measured the signals on the 1.8V side.

It seems that the clock voltage drop issue occurs not only when there are transition the CMD/DATA lines, but also when these lines are idle.
See Pic below

Hi Matan,

Schematic in first post mentions 10kohm pullups on all ports on A-side, though your latest response mentions no pullups/ pulldowns on either side. Which is correct? Can you please verify if power supply is not clamping and providing ample current for device to operate, especially when all ch are toggling? How many devices is this anomaly seen in? 

Regards,

Jack

Hi Jack

In the begging I used 10kohm- 1s pics
Afterward yo advise me to remove the PU and I did so- 2s pics

I have measure the 1.8V & 3.3V LS PS directly on the 100nF coupling capacitors- I didn't saw any voltage drop

I have test 2 different board with this IC and both have this issue

1.8V LS measure:

Hi Matan,

Matan Rumpler said:

I have measure the 1.8V & 3.3V LS PS directly on the 100nF coupling capacitors- I didn't saw any voltage drop

How about the supply itself? Any chance that the current is limited due to max current draw of device during switching multiple channels simulatenously by chance?

I find it odd that the clock signals function fine until the data signals come in. How are the trace length conditions and possibility of crosstalk concern here? The clock freq. appears quite fast as well, (>50MHz) can you confirm the value? 

Regards,

Jack

Hi

The main PS also not limited
Clk frequency= 48Mhz(
I see this issue only the 1V8 side. the distance between LS and CC3301 is short (500mil approx)




Thanks
Matan

Hi 

Can you explain way 35MHz?

If I underset correct:

I have 4 Data lines X 48MHz Clock = 200Mbps, meaning I'm out of the Max Data Rate

So for my case I need:

70Mbps / 4 Data lines  = 17.5MHz Clock

Thank you

Hi Matan,

The max data rate is specified for channel, so the highest supported per  channel is 70Mbps/35MHz at this voltage corner. Any updates on the SI if we decrease the CLK frequency?


Regards,

Jack 

Hi 

We change clk to 15MHz

Didn't see any improvement

Thank you