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SN74LVC1G175: Output changes also at the falling clock edge?

Part Number: SN74LVC1G175
Other Parts Discussed in Thread: SN74HCS74

Tool/software:

Hi TI, 

I have a problem with the 74LVC1G175 which I have being using in a design. After investigating its behavior I have found that it not only changes the output on the rising edge on the clock input, but it also changes the output at the falling edge aswell.The yellow top curve is the clock (pin 1), and the bottom green is the output (pin 4). 

 


Here is a picture of the truth table form the data sheet of SN74LVC1G175DCKR, where it can be seen that only the rising edge should result in changes on the output. 



I am unsure if there are any specific details I should be aware of? It is powered by 3.3V, and coupled as a toggle F-F with a N-channel MOSFET connected between the output and the data input. 


Thanks in advance. 

  • Please zoom in on a falling edge. What is its slope? Is it below the specified Δt/Δv limit?

  • Hey Clemens, 

    Thank you for your reponse. I can see in the datasheet that a recomended maximum value for the Δt/Δv is 10ns/V for 3.3V. 
    Measuring the rising edge I got 217ns/V (for the 2V-0.8V range), but for the falling edge it was 16.5us/V! for the same voltage range. I changed the pull-down resistor on the clock pin, and got it down to 2.25us/V, and now the circuit works as expected. 

    I can see in the datasheet the recommended maximum time is 10ns/V, but I am still running the falling edge way above this value. Do you have any advice on a maximum limit? The circuit is working as expected, meaning 2.25us/V must be good enough, but I am afraid if it will fail under certain conditions (e.g. temp).

    Br. Thomas  

  • The maximum limit is the limit specified in the datasheet.

    Use a flip-flop with Schmitt-trigger inputs (e.g., SN74HCS74), or add a Schmitt-trigger buffer.