SN74LVC1G175: Output do not match the truth table

Fabio Gou

Part Number: SN74LVC1G175

Tool/software:

Hi Experts,

From the datasheet:

The D Flip-Flop is edge triggered.

When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge.

Why the below picture shows the wrong test results?

is there any possible reason?

0 Clemens Ladisch 3 months ago

Guru 317000 points

Please zoom in on the falling CLK edge. I suspect that it violates the Δt/Δv limit.

0 Fabio Gou 3 months ago in reply to Clemens Ladisch

My question is that in CLK falling edge, the output pin (Q) should not be changed? is it right?

Will the Δ t/Δ v limit affect this?

0 Clemens Ladisch 3 months ago in reply to Fabio Gou

Guru 317000 points

A falling edge should not affect the output. But a slow edge will result in oscillations, i.e., multiple falling and rising edges.

0 Fabio Gou 3 months ago in reply to Clemens Ladisch

Is there any minimum Δt/Δv requirements description in the datasheet?

I can only find this.

0 Clemens Ladisch 3 months ago in reply to Fabio Gou

Guru 317000 points

Δt/Δv describes the slope of the edge. An edge that needs more than 10 ns to change by 1 V would be too slow.

0 Fabio Gou 3 months ago in reply to Clemens Ladisch

Hi Experts, the green one is CLK. The yellow one is OUT.

Could you help to comment on this?

0 Clemens Ladisch 3 months ago in reply to Fabio Gou

Guru 317000 points

You should use a higher sample rate.

But the edge is much too slow. How exactly is this signal generated? Are there any other components (such as capacitors) connected to this line?

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