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SN74LVC1G175: Output do not match the truth table

Part Number: SN74LVC1G175

Tool/software:

Hi Experts,

From the datasheet:

The D Flip-Flop is edge triggered.

When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge.

Why the below picture shows the wrong test results?

is there any possible reason?