SN74HCS72: Holding a Data Bit into Latch

Aditya Kumar Singh

Prodigy 30 points

Part Number: SN74HCS72

Tool/software:

Hi E2E Team,

I have below requirement-

1) There is an active low error signal (pulse: high -> low (100ms) -> high) input to the system

2) There can be a single pulse or multiple pulses based on the pre-defined specification

3) The system requirement is to have an error LED for visual indication and the error LED should be turned on permanently on the 1st falling edge

4) Plan is to drive the error LED enable circuit from a latch because, latch can hold the data at o/p even if the data is changing at the i/p pin

Below are the queries-

1) Please let me know weather SN74HCS72 can be used for the above implementation?

2) Please suggest if there is suitable latch other than SN74HCS72, which can suffice the above requirement?

3) Is there any other way other to implement the above requirement?

Regards,

Aditya

5 months ago

0 Clemens Ladisch 5 months ago

Guru 318050 points

You need a flip-flip with /PRE/CLR inputs (like the SN74HCS72), or a set/reset latch. Connect an active-low reset signal to /CLR, and the error signal to /PRE. CLK and D must be tied to a valid logic voltage, but do not matter otherwise.

0 Aditya Kumar Singh 5 months ago in reply to Clemens Ladisch

Prodigy 30 points

Hi,

Thankyou for your response. LT Spice simulated is done for below scenarios:

Simulation result:

Scenario 1 & 2: Q -> High, Q_N-> Low

As per "Table 1. Function Table" from SN74HCS72 datasheet and above schematic, expected result is:

Scenario 1 & 2: Q -> Low, Q_N-> High

Simulation results are the opposite of the expected results. What are your thoughts here?

Thanks,

Aditya

+1 Clemens Ladisch 5 months ago in reply to Aditya Kumar Singh

Guru 318050 points

There is no reset signal in your simulation. The power-up state of a flip-flop is undefined.

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SN74HCS72: Holding a Data Bit into Latch