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SN74LVC2G74-Q1: CLOCK pin with PULLUP or PULLDOWN

DAVID SABALESKY
Prodigy 225 points
Part Number: SN74LVC2G74-Q1

Tool/software:

Hello Forum,

I have DFF with /CLOCK pin connected to an FPGA.

Is it advisable to bias the /CLOCK pin with a PULLUP or PULLDOWN resistor?

This is mainly to address start up glitches.

With PULLDOWN, leading edge prevails and with PULLUP the trailing edge triggers the input /CLOCK.

I am curious to what maybe the better option even for normal operation.

Are there any advantages or disadvantages for noise immunity in either case?

Thank,

David

  • 0
    Guru 316780 points

    The initial state of a flip-flop is undefined. The only way to get a consistent power-up state is to connect /PRE or /CLR to a reset signal.

  • 0 in reply to Clemens Ladisch
    Prodigy 225 points

    Hello Clemens,

    /PRE=H and /CLR is tied to reset signal. The question is more related to general start up as well as any noise in the system which can trigger the /CLK input.

    When using Pulldown, the leading edge triggers /CLK, low-high-low. When using Pullup, the trailing edge triggers /CLK, high-low-high.

    Are there any advantages or disadvantages in either case? especially when noise is in the system.

    The circuit I have designed has /PRE = H, and /CLR is a steady state CMOS input from another circuit and just after POR, /CLR goes low to keep Q = L. 

    This is a failsafe circuit when our FPGA and DSP are booting up.

    Any advice is greatly appreciated.

    Sincerely,

    David

  • 0 in reply to DAVID SABALESKY
    Guru 316780 points

    As long as /CLR is low, what happens on the CLK pin does not matter.

    In what sequence do the supplies for the FPGA, the pull-up resistor, and the flip-flop power up?