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SN74LV393A: uncertainty of first utput after asynchronous clear

Alexander Malmberg
Prodigy 10 points
Part Number: SN74LV393A

Tool/software:

What will the Q_A output be at the first negative edge of CLK after a clear?

When examining the timing diagram (Figure 6.12) in the datasheet, it appears that CLR goes low at the same time that CLK has a negative edge. This makes it unclear whether the first Q_A output after CLR goes low will be 0 or 1.

If the CLR input were to go low half a clock cycle earlier, would the Q outputs remain the same, or would they shift one clock cycle earlier?




Thanks

  • +1
    Guru 316940 points

    The CLR input is asynchronous, so it must go low before the negative /CLK edge that you want to happen. This is specified with the setup time; if the two edges happen at the same time, the behaviour is not predictable. The timing diagram shows such an undefined case; it would be correct if the CLR input would go down after the negative /CLK edge.

  • 0 in reply to Clemens Ladisch
    Prodigy 10 points

    Thanks for the answer, well explained. I interpret it as: Q_A (and all other Qs) stay at 0 after CLR goes low, and then Q_A goes high at the next falling edge of CLK.