TPLD-ICS: Incorrect simulation of counters

Clément Letonnelier

Part Number: TPLD-ICS
Other Parts Discussed in Thread: TPLD2001

Tool/software:

Hello,

From the figures of the datasheet showing the counter output timing example when using the high level reset, the output OUT of the counter is shown as being equal to 0 when the reset is high.

However, when simulating the following:

We observe the following:

The reset is high but the OUT output of the counter is high while we would have expected it low from the datasheet.

Is it a simulation bug ?

Clément

3 months ago

0 Malcolm Lyn 3 months ago

TI__Mastermind 26290 points

Hi Clement,

No, this was a hardware bug that we changed in one of the first revisions of the hardware. I have not fixed the simulation to match this behavior yet.

Best,

Malcolm

0 Clément Letonnelier 3 months ago in reply to Malcolm Lyn

Expert 2816 points

Hi Malcolm,

It's a bit annoying, we are trying to design and pre-verify the design with simulations as the TPLD2001 EVM is not out yet.

Do you have any ETA for the fix ?

Thank you,

Best regards

Clément

0 Malcolm Lyn 3 months ago in reply to Clément Letonnelier

TI__Mastermind 26290 points

Hi Clement,

This fix would not become available until at least our next ICS release which is probably not for another 3 months.

Best,

Malcolm

0 Clément Letonnelier 3 months ago in reply to Malcolm Lyn

Expert 2816 points

Malcolm,

That's quite far away.

Would you be able to provide me with a modification similarly to the watchdog issue ?

Or a non official ICS release ?

Best regards,

Clément

0 Malcolm Lyn 3 months ago in reply to Clément Letonnelier

TI__Mastermind 26290 points

Hi Clement,

This fix is a little higher effort since I need to get the newer code we used in the actual design to implement it in simulation. I will try to get it to you by next week.

Best,

Malcolm

0 Clément Letonnelier 3 months ago in reply to Malcolm Lyn

Expert 2816 points

That would great thanks.

Clément

0 Malcolm Lyn 3 months ago in reply to Clément Letonnelier

TI__Mastermind 26290 points

Ok, I will work on getting a fix out. I'm travelling to China on Sunday and will be there the entire week for a work conference, but I hope to be able to deliver this by next Friday, if not sooner.

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TPLD-ICS: Incorrect simulation of counters