Tool/software:

I'm using the SN74LVC1G74 D-type flip-flop IC. The issue I'm facing is that the output Q is not behaving as expected. Specifically:

• When the Clock is high and MR (Master Reset) is clear (high), the output Q is low
• But after clearing MR (setting it low), if I bring the Clock low (falling edge), the output Q goes high again, which is unexpected. I expect it to go low.

Here are the steps I followed:

Data	MR	Clock	Output (Q)
H	H	Low	Low
H	H	Rising edge	High
H	L	High	Low
H	H	High	Low
H	H	Falling edge	High  (Expected: Low)