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TXV0108: Will I/O pin outputs be glitch-free during all combinations of VCCA/VCCB power-up sequences?

Benjamin Kropf
Prodigy 10 points
Part Number: TXV0108

Tool/software:

I couldn't find this clearly mentioned in the TXV0108 datasheet, so I thought I would ask here. Thanks in advance!

Here is my application:

  • During normal "powered-up" operation:
    • VCCA connected to a 1.8V power rail.
    • VCCB connected to a 3.3V power rail.
    • DIR connected to VCCA voltage (possibly through pull-up resistor) so that direction will always be fixed from A to B.
    • OEn pin connected to VCCA through pull-up resistor so it is de-asserted by default until some other device will drive it low (such as, some sort of SYSTEM_READYn type signal).
  • Power-up/down sequences are like this:
    • Relationship between VCCA and VCCB coming up/down are "unknown"
    • DIR will be connected to VCCA through pull-up.
    • OEn will be connected to VCCA through pull-up (or in power-down scenario, OEn may be driven LOW).

Given all of the above info, could I expect that there will never appear any "high" or "non-zero" output glitches appearing on any of the A/B I/O pins when the following is true:

  • All A I/Os are driven to GND (Low) or have a pull-down.
  • VCCA comes to 1.8V and VCCB comes up to 3.3V and the order/timing of the two power rails coming up is "undefined".
  • DIR is at 1.8V (that is, it is connected to VCCA).
  • Finally, at the end OEn is driven from Pull-up High (VCCA=1.8V) state to LOW (asserted) state.

In this application it is important that there should be no non-zero voltage glitches occurring (on B I/Os) during the power-up/power-down sequences and I just want to make sure that this TXV0108 part would guarantee this as long as OEn is connected to VCCA voltage during power-up/power-down

To go further, would glitches be prevented also in the case where VCCA is at 1.8V, OEn is at 0.0V (asserted) and VCCB falls from 3.3V to 0V. That is, in the power-down case, are glitches prevented if VCCB supply is removed first while OEn is asserted? I am hoping the B I/O outputs make a seamless transition from A->B driving state to HiZ state without doing some "High" out glitch in the middle of the transition.

Thanks!

Ben

  • 0
    TI__Mastermind 22420 points

    Hello Ben,

    The TXV0108 has two features: Vcc Isolation and Vcc Disconnect.

    If either supply reaches 0V or is left floating, I/Os will become Hi-Z. This prevents the outputs from producing any non-zero glitches.

    In additional to the features I mentioned above, this part has a more robust power sequence circuitry that prevents output glitches from occurring, even in situations where OE is pulled to GND.

    Regards,

    Josh