CD4013B: Faster SR latch with non-inverted and inverted output

I know it is theoretically possible to build any latch or flip-flop using basic gates, but can I get the same transient performance as a proper latch or flip-flop?

I am actually more worried about the stability under transients rather than propagation delay, since external connections between the NOR gates introduce parasitics. But then I guess its hard to predict what may happen as this all depends on my layout, right?

With the SR latch created with two NOR gates, is there a possibility of glitches during power-up? For a (non-inverting input) SR latch, the non-inverted output should be low if both inputs are low. However, since the input of gate A is connected to the output of gate B, is it possible for the non-inverting output to be momentary high during startup, before gate B can respond to its input (or vise versa), even if both inputs are pulled low?

I am worrying about this because the output of a NOR gate would be high unless at least one of the input is high. But before power-up,the input of every gate is low. There appears to be a possibility of unwanted glitch somewhere in the power-up process. Is my concern valid?

Also, is there any 2-channel NOR gate chip that can handle 6V VCC?

Thank you