TPS36-Q1: Max sink current/capacitive load of RESET pin of TPS36CD40EACDDFRQ1

Part Number: TPS36-Q1
Other Parts Discussed in Thread: TPS36

Tool/software:

Hello,

We are using TPS36CD40EACDDFRQ1 as a watchdog timer. To make it little robust for glitches, on the RESET (open drain) line, we have used a 100nF capacitor along with a pull-up resistor. There is another 10nF capacitor near the MCU reset pin.

Once the WDT asserts reset, we are seeing issue on WDI line and MCU is not able to reset the WDT device. It is simple pin to pin connection with MCU pin configured as GPIO in push-pull-mode. However, the issue seems to disappear when we try to probe (with DSO or DMM) this net. It also disappears if we connect a pull-up OR pull-down resistor. It looks like some ESD related latch-up issue with pin floating and needing assistance to either bring it up or down. First we suspected ESD issues but confirmed that the parts are received directly from TI and have been assembled in our EPA  plants.

Now I wanted to see how much current RESET pin is capable of sinking. I could not find that information in the datasheet. Please help me with this figure and the maximum capacitive load I can have it on that pin.

  • The datasheet mentions about current ±20mA on RESET pin as a maximum absolute rating. However, I cannot co-relate with maximum capacitive load it can handle. So please let me know the maximum capacitance at this pin we can have in the design.

  • Hi,

    1. Could you please help rephrase the issue? Is it related to the WDO asserting not-asserting? 
    2. Could you please help to share a schematic?

    We do not specify a maximum capacitive load on the RESET/WDO as we recommend not placing a capacitor on this net since it will conflict with the output assert time of the device.

    Thanks,
    Joshua

  • Let me try,

    1. Interface between MCU and WDT seem to work well initially. Once we make MCU, NOT assert WDI signal we get RESET/WDO pulse from WDT as expected. But after this, MCU stops asserting WDI signal. We have confirmed that there is no issue with SW or port pin configuration. We don't see this issue when we 'touch' that pin with DMM or DSO probe. This issue also disappears if we have either pull-up or pull-down resistor on that path. I am suspecting some internal latch-up issue once WDT asserts RESET/WDO (having to discharge 110nF!).

    2. Schematics is attached

    Yes, but during validation, we had to connect a small capacitor to pass tests like BCI. So I would like to know if my assessment on this issue is correct and what is the maximum capacitance we could have on this pin.




  • To confirm if this is a device damage because of heavy (110nF) capacitor discharge at the RESET/WDO pin, we mounted new TPS36-Q1 device on a board. We also removed 100nF capacitor on that board before. But the issue persists failing the WDI communication after we make TPS36-Q1 assert reset pulse over RESET/WDO pin.

  • Hi all, Olivier here filling up for Dierk who is ooo as FAE.

    Back to basic  here are below 2 oscilloscope captures, exact device used is TPS36CD40EACDDFRQ1 (device marking NLHOV) : can you please confirm that the timing between 2 reset when the TPS36 may not be receiving any WDI is expected ? can you please break it down to see what orderable we may need to tweak this or that knob ?

    Also one of the theory is that the MCU doesnt have time to boot up and send the WDI before the TPS36 issues a reset again

    working :

    not working (WDI cant be probed, as when probed not only does it look correct, but the system is back and running up until we remove the probe and the MCU resets again)

  •  can you please send your layout ?

  • Hi Olivier, ,

    Thank you for the detailed information.

    Per your call with Sila it looks like adding any sort of pullup/pulldown fixes the issue. Due to this it seems the MCU has enough time to startup and provide the pulse. Like  was stating it looks like a latchup condition, however this should not be possible given the input topology of this WDI pin. Regarding this I will share additional TPS36-Q1 device information over email.

    As a solution for the time being I would recommend the pullup resistor be populated as this fixed the issue and provides no concerns with our device. It would be best if we could also remove the TPS36CD40EACDDFRQ1 device from the board and test it on an EVM to isolate if this issue is due to the watchdog IC. 

    Thanks,
    Joshua