TXS0108E: Please confirm maximum data rate for SDIO interface.

Part Number: TXS0108E
Other Parts Discussed in Thread: TXS0206A, LSF0108

Tool/software:

Dear TI experts,

My customer tests the performance of TXS0108E on their own PCB.

They test it for level transfer between eMMC memory and MCU.

Schematic is made using push-pull topology, so I think that it should be supported up to 110Mbps.

But regarding to the results of my customer,

- 4bit communication (25MHz) : working well.

- 8bit communication (25MHz, 50MHz) : not working.

And here are my questions ;

1. 110Mbps data rate means that the rate of total bit?

(i.e. 25Mbps(MHz) for 4bit communication, 25MHz * 4bit = 100MHz)

Or 110Mbps data rate support each bits?

2. Could you recommend bidirectional voltage level shifter which can work with SDIO 8bit communication? (should work with 50MHz clock frequency)

I attach the chstumer's schematic which used TXS108E.

e-MMC.pdf

Please check this issue. THanks.

Best regards,

Chase

  • Hi Chase,

    1. Your understanding is correct, the max data rate is given per channel, so each channel is capable of the 110Mbps support. 
    2. The TXS0206A is optimized for SDIO level shifting applications. 

    If you have any waveforms showing the anomaly that would be helpful to debug as well. Please note that this device does not perform well when output loading conditions are too heavy. Consider using shorter connector lengths and cables to reduce parasitic capacitances as much as possible. 

    Regards, 

    Jack

  • Dear Jack,

    Thank you for your support.

    1. Then how can I understand this results? (8bit communication_25MHz or 50MHz : not working)

    What do you think about the reson of this results? Is it related to layout or other part of schematic?

    2. The device you recommended (TXS0206A), and it supports clock up to 60MHz and data up to 60Mbps. I think it is little low for my customer.

    Do you think LSF0108 would be work for eMMC memory? It is bidirectional and supports up to 200Mbps.

    Please check this issue. Thanks.

    Best regards,

    Chase

  • Hi Chase,

    1. Higher output loads (from PCB traces, target devices and connector lengths) will result in negative impact on the SI of the waveform, i.e transmission line effects such as ringing/ oscillations. Please note that the max data rate was tested given output Cload = 15pF.

    2.Can you elaborate how that is the case? 60MHz support is sufficient enough for the 50MHz clock here, unless otherwise DDR mode is needed and the data line is needing 120Mbps support as well. (Here, 1MHz= 2Mbps can be used as conversion). LSF would not be the best choice here. 

    Regards,

    Jack