Hello,
In my new design I want to use the SerDes SN65LV1023A and SN65LV1224B with one clock of 30MHz.
I'm going to use the component in Open-loop and I will use All the 10-bit and I don't see problems to syncronize the 2 components with the start bit and stop bit (Random-Lock Synchronization).
The question is: once the system is locked and reading well all the bits, occurs a problem if the value of 10 bits is the same during 100ms? (the clock is also 30Mhz). I need to implement systems like bit-stuffing?
Thanks!
Marmota