SN75LVDT1422 Serdes in clock burst operation?

Phil Lizzi

Intellectual 2605 points

Other Parts Discussed in Thread: SN75LVDT1422

Can the SN75LVDT1422 SERDES operate with a burst clock (see customer inquiry, below)?

Will the PLL achieve a faster lock if the clock burst off ime is under the typical PLL lock time?

Customer's Application

GPN: SN75LVDT1422

LGC, Semiconductor Technical Support, www-k.ext.ti.com, SN75LVDT1422

Question about SN75LVDT1422 Hello, I am considering the use of the 1422 in a new design. One of the questions that I have about using this part is how it will respond to my clock signal. In this application, my clock comes in bursts. I am concerned that with a 'gated' clock, that this part may not work. Can you confirm or deny my suspicions? Clock rates are on the order of 100 kHz to 200 kHz depending on the application. Dead times between clock bursts are on the order of 82 uS to 2.9 mS.

Thanks,

Phil

over 15 years ago

0 Miguel Robertson over 15 years ago

TI__Guru 62920 points

The PLL will always try and track the input clock. When there is some dead time between clock bursts, the PLL will fall out of lock and will take some time to find the clock again once it is reapplied. A designer can correct me if I'm wrong, but I believe the PLL lock time would depend not on the clock off time but rather on the initial phase relation between the input clock and the PLL.

If the input clock signal is 100 kHz to 200 kHz, it seems that the LVDT1422 would not be an ideal choice anyway. The minimum recommended clock frequency for this device is 10 MHz.

Regards,

Max

Logic

Logic forum

SN75LVDT1422 Serdes in clock burst operation?