• State TI Thinks Resolved
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 20 subscribers
  • Views 12 views
  • Users 0 members are here
Support feedback
Options
Options
Related

SN74LVC07A: Schematic check

EASON *.*
Prodigy 30 points
Part Number: SN74LVC07A

Tool/software:

Hi Sir:

The current test circuit is shown above.

We found that when the input signals at pins 1/3/13 are all pulled high, the measured output signals at pins 2/4/12 are all low.

Why is the measured signal level low when pin 2 is pulled high to LDO1_OUT (1.8V) and pin 12 is pulled high to SW2_OUT (1.8V) through a resistor?

Please advise on this situation.

Thanks!

Best Regards

  • 0
    TI__Genius 9591 points

    Hi Eason,

    It looks like pins 5 and 9 are floating. This means the device registers them as effectively random. For your design, I'd recommend pulling them high. If either of them are registered as low, your output will be pulled down.

    Regarding pin 12, what is the state of pin 11 while you are testing? If either pin 11 or pin 13 are low, the output is expected to be low.