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SN74LV4320 Power Down Input Pin Specs

I am taking over a prototype design that interfaces a SN74LV4320 to a PXA270. In this design there are situations where the VCC_S supply is shutoff while the SD/SA/control lines are still active. For reference Master_Enable will be driven high however it probably doesn't matter.

The spec is not entirely clear in this area. The Absolute Max specs seem to indicate this is OK, but I wanted to verify that driving the input pins are acceptable with the power supply disabled.

Thanks,

Bob